1. Field of the Invention
The present invention relates to an inductor which is formed in a semiconductor integrated circuit and a method of fabricating the inductor.
2. Description of the Related Art
A conventional inductor provided in a semiconductor integrated circuit is formed on the same layer as the interconnection of the topmost layer of a multilayer interconnection formed by a damascene process (see Japanese Patent Laid-Open No. 2001-267320). FIG. 1 is a cross-sectional view of a semiconductor integrated circuit including a conventional inductor. Wells 2 and 3 are formed in the surface of a substrate 1, and a pair of high-concentration diffusion layers 6 of an MOS transistor and a low-concentration diffusion layer 7 lying between the diffusion layers 6 are formed in an area which is defined by device isolation regions 4 and 5 on the surface of the well 2. A gate insulation film 8 is formed on the substrate between the diffusion layers 6, and a gate electrode 9 and a side-wall insulation film 10 on the sides of the gate electrode 9 are formed on the gate insulation film 8. This provides an MOS transistor with an LDD (Lightly Doped Drain) structure.
A multilayer interconnection is formed on the substrate 1. Specifically, a first interlayer insulation film 11 is formed on the substrate 1, and a first interconnection layer 12 is formed on the first interlayer insulation film 11. The first interconnection layer 12 is formed by the following process. First, as shown in FIG. 2A, after a contact hole 21 is formed in the first interlayer insulation film 11, an insulation film 11a is formed on the first interlayer insulation film 11. Then, as shown in FIG. 2B, a groove 22a for an interconnection 22 is formed in the insulation film 11a by forming a resist pattern on the insulation film 11a by photolithography and then dry-etching the insulation film 11a with the resist pattern as a mask.
Next, as shown in FIG. 2C, a thin metal film 32 (TaN film or the like) to be a plating electrode is formed on the surface of the bottom and sides of the groove 22a for the interconnection 22 by sputtering or the like, and a barrier metal layer 23 is formed on the bottom of the groove 22a after which Cu is buried in the groove 22a for the interconnection 22 by plating Cu with the metal film 32 as a cathode. In this case, Cu is also deposited on the insulation film 11a. 
Thereafter, as shown in FIG. 2D, Cu on the insulation film 11a is removed by CMP (Chemical Mechanical Polishing) to expose the insulation film 11a and planarize the surface of the insulation film 11a and the surface of the Cu buried in the interconnection groove 22a. As a result, a buried interconnection 22 is formed in the first interconnection layer 12.
Using the damascene method, likewise, a second interlayer insulation film 13 is formed on the insulation film 11a, a contact hole 24 is formed in the second interlayer insulation film 13, and an interconnection 25 of a second interconnection layer 14 is formed on an insulation film 13a formed on the second interlayer insulation film 13. Further, a third interlayer insulation film 15 is formed on the insulation film 13a, a contact hole 26 is formed in the third interlayer insulation film 15 and an interconnection 27 of a third interconnection layer 16 is formed on an insulation film 15a formed on the third interlayer insulation film 15. Furthermore, a fourth interlayer insulation film 17 is formed on the insulation film 15a, a contact hole 28 is formed in the fourth interlayer insulation film 17 and a topmost interconnection 29 of a topmost interconnection layer 18 is formed on an insulation film 17a formed on the fourth interlayer insulation film 17. The barrier metal layer 23 is also formed on the bottom of the topmost interconnection 29 and another barrier metal layer 31 is formed on the top of the topmost interconnection 29. A protective film 19 is formed on the entire surface of the resultant structure.
In a semiconductor integrated circuit which has the conventional inductor, therefore, the coil-like inductor 30 is formed simultaneously at the time of forming the topmost interconnection 29 of the topmost interconnection layer 18. That is, at the time of patterning the groove for the topmost interconnection 29 of the topmost interconnection layer 18 in the insulation film 17a by photolithography, the groove for the inductor 30 which is a coil-like interconnection is patterned simultaneously. Then, after a thin film for the plating electrode is formed by sputtering, the Cu film is formed by electrolytic plating in such a way as to be buried in that groove, then the surface is subjected to CMP to planarize the surface.
In the conventional semiconductor integrated circuit, the inductor 30 is formed together with the topmost interconnection 29 on the topmost interconnection layer 18 of the multilayer interconnection layer, formed by the damascene method, in the above-described manner.
Because the inductor 30 is formed at the same time as the topmost interconnection 29 by the damascene method in the conventional semiconductor integrated circuit, however, the thickness of the inductor 30 is limited by the thickness of the topmost interconnection layer 18. There is a limit to the thickness of the topmost interconnection layer 18 due to the restrictions on the fabrication process. As shown in FIG. 2D, “dishing”, a phenomenon which produces a recess portion as the center of the surface of the interconnection is etched, occurs in the above-described CMP process in the damascene method. The wider the interconnection is, the more noticeable this “dishing” becomes. This puts some restriction on the width of the interconnection of the inductor 30.
Because of the restrictions on the interconnection width and the film thickness, the conventional inductor cannot have a large cross-sectional area. The conventional inductor disadvantageously has a high resistance which makes it difficult to improve the Q value that indicates the performance of the inductor.
Further, the surface, 33, of the interconnection 22 undergone CMP is recessed by dishing as shown in FIG. 2D, resulting in poor film planarization. Due to a variation in conditions for CMP, the uniformness of the film thickness of the inductor is poor, which is likely to cause a variation in the characteristics.